1. Technical Field
The present invention relates in general to the field of computers, and, in particular, to cache memory in a computer system. Still more particularly, the present invention relates to an improved method and system for accessing a cache line using a stored decoded address.
2. Description of the Related Art
The use of data caches for performance improvements in computing systems is well known and extensively used. A cache is a high speed buffer that holds recently used data (including instructions) from system memory.
Data in the cache is identified and located using the system memory address for the data. The system memory address contains most significant bits (MSBs) and least significant bits (LSBs) in the respective left and right portions of the address. The MSBs can logically be viewed as a pointer to a starting position in system memory, and the LSBs, when concatenated with the MSBs, provide an offset to complete the address. In cache memory addressing, the MSBs are called “tags” and the LSBs are called “indexes.”
Each index identifies a line (block) of cache memory. The tag is used to confirm that the line contains data from a particular address in system memory. That is, the tag and index are concatenated for comparison to the system memory address to confirm that the cache line contains data assigned the system memory address.
Level 1 (L1) cache has relatively few cache lines, typically from 64 to a few hundred. Each cache line contains many words (the largest number of bits of data that the computer can handle internally, typically 64 bits). Typically, each cache line contains 32 words (128 bytes).
To access a particular cache line, address generation logic transmits a set of enabled signals that result in the contents of the particular cache line being transmitted to a set of output pins. The signal to the cache line is the result of a decoding of the cache line's index to generate the signal. That is, the pre-decoded form of the index is input into a decoder that has an output of multiple (typically 64) pins. Each unique index results in one and only one of the decoder's output pins having an enable signal.
FIG. 1 depicts a typical configuration of prior art logic for selecting a cache line. An instruction 100 contains an operand code (OPCD) 102 and a displacement 104. Register file 106 contains multiple registers, including Register A (RA) and Register B (RB). RA contains the base address and RB contains the offset to the base address for the data requested. That is, RA contains a pointer to the block of system memory containing the requested data, and RB contains an offset, defined by instruction 100, that completes the memory address containing the requested data. Alternatively, RA contains the base address and displacement 104 directly describes the offset to the base address for the data requested.
Adder/ALU 108 combines the base address from RA and the offset (from RB or displacement 104) and sends the sum result (address) to a Target Register (RT). Extracted from the RT is the index 110 and offset 112 for the word (chosen by offset 112) in the correct cache line in L1 Cache 116. Decoder 114 decodes the six lines of cache address index 110 and outputs a signal on one of the pins in the output 64-way line selector 120. Offset 112 is decoded within L1 cache 116 to select the desired word from the line selected by 64-way line selector 120.
The system illustrated in FIG. 1 is burdened with the delay of adding two operands together and then decoding the cache address index 110 every time a cache line is accessed using the logic shown in grouping 122. Therefore, there is a need for a system that avoids such a delay.